The invention lies in the field of circuit technology and relates, more specifically, to an analog multiplier circuit for the multiplication of two differential signals.
Analog multipliers multiply two differential signals together, with the result that the multiplied signal can be drawn off at the output of an analog multiplier. Analog multipliers are used in mobile radio applications, for example. In order to form the intermediate frequency, in the case of the GSM mobile radio standard, for example, the reception signal coupled into the antenna is preamplified and multiplied by a local oscillator signal in an analog multiplier or down-converter. As a result, a multiplied signalxe2x80x94the intermediate-frequency signalxe2x80x94is available at the output of the analog multiplier for further processing.
An analog multiplier of the generic type is known as a Gilbert cell or Gilbert multiplier cell and is described for example by Gray and Meyer in xe2x80x9cAnalysis and Design of Analog Integrated Circuitsxe2x80x9d, third edition 1993, John Wiley and Sons, on pages 667-81. The Gilbert multiplier circuit is constructed from bipolar npn transistors. An emitter-coupled transistor pair is connected in series with two cross-coupled, emitter-coupled transistor pairs. The Gilbert cell allows the multiplication of two differential signals, whereby four-quadrant multiplication is possible. The Gilbert cell described has the disadvantage that it has only a very small linear range. The DC transfer characteristic of the Gilbert cell is the production of the hyperbolic tangent functions of the two differential input voltages. However, the hyperbolic tangent function is linear only for small arguments, that is to say small differential voltage values. It is only in the linear range, however, that the differential voltage signals are processed further in a manner free from distortion by the multiplier.
Mobile radio systems are increasingly being used in motor vehicles. In the case of car telephones, for example, in whose reception path analog multipliers are used as down-converters, there is a requirement for a higher linearity or a greater linearity range of the mixer.
The object of the present invention is to provide an analog multiplier which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which provides for higher linearity.
With the above and other objects in view there is provided, in accordance with the invention, an analog multiplier, comprising:
two first transistors having gates connected to one another, the first transistors being MOS transistors enabled to receive a first differential signal;
two second, emitter-coupled transistors;
two third, emitter-coupled transistors cross-coupled with the two second transistors;
one of the first transistors being connected in series with the two second transistors and another of the first transistors being connected in series with the two third transistors;
the two second and the two third transistors being configured to receive a second differential signal and to output a third differential signal as an output signal thereof.
In other words, two first transistors are MOS transistors whose gates are connected to one another. The MOS transistors are used as input stage in order to increase the linearity range of the analog multiplier.
In other words, the analog multiplier has two first transistors, which are connected to one another and to which a first differential signal to be multiplied can be fed. A respective emitter-coupled transistor pair is connected in series with the two first transistors, in each case two second transistors whose emitters are connected to one another and two third transistors whose emitters are connected forming a transistor pair. These transistor pairs are cross-coupled to one another. A second differential signal to be multiplied can be fed to the base terminals of the second and third transistors. The multiplied signal can be picked off at the collector terminals of the second and third transistors. The above-described circuit for forming an analog multiplier has the advantage of a higher linearity or a greater linear range.
In accordance with an added feature of the invention, the MOS transistors are connected to ground via respective resistors.
In accordance with an additional feature of the invention, a capacitor is connected between the gates of the MOS transistors and ground. A bias voltage can be set at this point.
In accordance with another feature of the invention, a cascode circuit is formed as follows: fourth transistors are respectively connected in series between one of the first transistors and the two second transistors and between the other of the first transistors and the two third transistors. This configuration has the advantage of combining the higher linearity with a low supply voltage.
In accordance with a further feature of the invention, the fourth transistors are connected to one another at a node, and a second capacitor is connected between the node and ground. A second bias voltage can be fed in at this node.
MOS transistors have parasitic capacitances between drain and source, and between gate and drain. At high frequencies, the path from the emitter nodes of the second transistors and from the emitter nodes of the third transistors to ground acquires a relatively low impedance if the fourth transistors are not used. The second differential signal which can be applied to the multiplier circuit generates, at the emitter nodes of the second and third transistors, as a result of a rectification operation at the base-emitter diodes of the second and third transistors, a common-mode voltage signal at twice the frequency of the second differential signal that can be fed in. This common-mode voltage signal generates a common-mode current signal since low-impedance paths are formed by the MOS transistors effected by parasitic capacitances. This common-mode current signal in turn generates a common-mode voltage signal at the output of the circuit, across a load resistor that can be connected, said common-mode voltage signal having a high signal amplitude if the load resistor is large. The high common-mode voltage signal is superposed on the useful signal at the output, that is to say on the third differential signal which can be picked off at the second and third transistors. The result is that the useful signal output level of the multiplier circuit already attains limitation before the actual linearity limit. An increase in the supply voltage reduces the limitation of the useful signal level at the output of the multiplier. The insertion of fourth transistors into the circuit prevents low-impedance paths from being formed, and, consequently, this circuit has not only the advantage of higher linearity but also the advantage of the low supply voltage. This is because, due to the dictates of the system, an increase in the supply voltage is often impossible or undesirable.
In accordance with an concomitant feature of the invention, the analog multiplier as summarized in the foregoing is provided in combination with a mobile radio system; the first differential signal is a reception signal, the second differential signal is generated by a local oscillator, and the third differential signal is an intermediate-frequency signal further utilized in the mobile radio system.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an analog multiplier, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.